References - 3.0 English

This section provides links to supplemental material useful to this document:

1. Vivado Design Suite: AXI Reference Guide (UG1037)
2. 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
3. UltraScale Architecture GTH Transceivers User Guide (UG576)
4. Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)
5. UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
6. UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)
7. AXI Memory Mapped to PCI Express (PCIe) Gen2 LogiCORE IP Product Guide (PG055)
8. DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
9. AXI Verification IP LogiCORE IP Product Guide (PG267)
10. 7 Series FPGAs Clocking Resources User Guide (UG472)
11. UltraScale Architecture Clocking Resources User Guide (UG572)
12. AMBA AXI4-Stream Protocol Specification (ARM IHI 0051A)
13. PCI-SIG Specifications (https://www.pcisig.com/specifications)
14. ISE to Vivado Design Suite Migration Guide (UG911)
15. Vivado Design Suite User Guide: Getting Started (UG910)
16. Vivado Design Suite User Guide: Designing with IP (UG896)
17. Vivado Design Suite User Guide: Logic Simulation (UG900)
18. Vivado Design Suite User Guide: Programming and Debugging (UG908)
19. Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
20. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)