Required Constraints - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The Bridge core requires a clock period constraint for the reference clock input that agrees with the REF_CLK_FREQ parameter setting. In addition, pin-placement (LOC) constraints are needed that are board/part/package specific.

See Placement Constraints for more details on the constraint paths for FPGA architectures.

Additional information on clocking can be found in the Xilinx® Solution Center for PCI Express (see Solution Centers).

Note: The reference clock input is refclk in Virtex®-7 devices and sys_clk_gt in UltraScale devices.