Revision History - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The following table shows the revision history for this document.

Section Revision Summary
11/16/2022 Version 3.0
Bridge Parameters Updated Top-Level Parameters table.
Interrupt Decode Register (Offset 0x138) Updated Interrupt Decode Register table.
Interrupt Mask Register (Offset 0x13C) Updated Interrupt Mask Register table.
Completion Timeout Updated Completion Timeout section.
Completer Abort Updated Completer Abort section.
07/22/2020 Version 3.0
AXI Bridge for PCIe Gen3 and DMA/Bridge Subsystem for PCIe in Bridge Mode Updated descriptions for Legacy Interrupts, MSI Interrupts, and MSI-X Interrupts
Root Port MSI Interrupt Decode 2 Mask Register (Offset 0x17C) and

Root Port MSI Interrupt Decode 1 Mask Register (Offset 0x178)

Updated interrupt_out_msi_vec* signal names in descriptions.
Tandem Configuration Updated Partial Reconfiguration to Dynamic Function eXchange.
07/16/2019 Version 3.0
Port Descriptions Reorganized port description information into individual tables per interface.
AXI Slave Interface and AXI Master Interface

Corrected port name and updated description for s_axi(b)_wuser and s_axi(b)_ruser.

Transaction Ordering for PCIe Updated details regarding relaxed ordering.
Completion Timeout Updated details regarding PCIe configuration read/write requests.
Basic Tab (DMA/AXI Bridge Subsystem for PCI Express in AXI Bridge Mode) Added MPSOC PL RootPort solution.
CCIX Interface Added appendix.
12/05/2018 Version 3.0
Product Specification

Added Gen4 support to the Minimum Device Requirements table.

Added clarifying note to axi_ctl_aclk signal description.

Added Configuration Register Attribute Definitions table to Memory Map section.

Designing with the Core Added Gen4 support to the Clock Frequencies and Interface Widths table.

Added Root Port System Reset Connection diagrams to the Reset section.

Added clarifying note to Receiving Interrupts section.

04/04/2018 Version 3.0
General Updates

Clarified that Tandem Configuration is not yet supported for Bridge mode in UltraScale+™ devices.

Product Specification

Added more detail to interrupt_out port description (in the Top-Level Interface Signals table in the Product Specification chapter).

Updated the axi_ctl_aresetn port default values Please refer to the description for more details and the available options.

Updated signal name and description for s_axi_ctl_awaddr/s_axil_awaddr, and s_axi_ctl_araddr/s_axil_araddr.

Added the msi_enable, msix_enable, and dma_bridge_resetn signals.

Major rewrite in the Memory Map section.

Added C_MSI_RX_PIN_EN, INTERRUPT_OUT_WIDTH, and SOFT_RESET_EN bridge parameters.

Updated Reserved addresses in the IRQ Block Register Space in the “DMA/Bridge Subsystem for PCIePCIe Register Memory Map” section.

Added Virtex® UltraScale+™ Devices with HBM (PCIE4C) minimum device requirements information.

Designing with the Core Changed C_PCIE2AXIBAR_n to C_PCIEBAR2AXIBAR_n (in the BAR and Address Translation section).

Added Interrupts section to Endpoint section, and Receiving Interrupts section to the Root Port section.

12/20/2017 Version 3.0
Designing with the Core

Added Clock Frequencies and Interface Widths Supported For Various Configurations figure to the .

Updated the Clocking Diagram (UltraScale+ Devices).

Example Design Added example design block diagrams.
Test Bench Added Example Use Mode section.
10/04/2017 Version 3.0
General Updates

Added the DMA/Bridge Subsystem for PCI Express in AXI Bridge mode information (UltraScale+UltraScale+ devices only) to this document (formerly in PG195).

Added two new register descriptions: Root Port Interrupt Decode 2 Register (Offset 0x160), and Root Port Interrupt Decode 2 Mask Register (Offset 0x164).

Added example design details: Xilinx AXI Verification IP attached to the AXI Slave Interface.

Upgrading Updated details.
Using the Xilinx Virtual Cable to Debug New appendix added.
04/05/2017 Version 3.0
Customizing the Core Added the new Debug Options parameters.
11/30/2016 Version 3.0
General Updates

Updated to reflect that the core supports Narrow Bust in 2016.4.

Added the Minimum Device Requirements section.

10/12/2016 Version 3.0
General Updates

Updated that the slave bridge is capable of handling up to 8 memory mapped AXI4 read requests with pending completions.

10/05/2016 Version 3.0
General Updates

Updated Bit[2] and Bit[28] to reserved bits in the Interrupt Decode Register and Interrupt Mask Register tables.

Added Bit[13] row to PHY Status/Control Register table.

Minor updates to the Link Down Behavior section.

Migrating and Upgrading Added the New Ports table to the Port Changes section (Upgrading in the Vivado Design Suite)
06/08/2016 Version 2.1
IP Facts Updated Maximum Payload Size to 512 in IP Facts.
Top-Level Interface Signals Added axi_aresetn, s_axi_ctl_awaddr[31:0], and s_axi_ctl_araddr[31:0] to the table..
Top-Level Parameters Removed C_INCLUDE_BAROFFSET_REG, added pf0_msix_cap_pba_bir to pf0_msix_cap_table_size to the table.
Updated Note Address Translation
General Updates Updated PCIe Miscellaneous Setting figure and GT Settings figure.
PCIe Miscellaneous Added MSIx Table Settings and MSIx Pending Bit Array Settings section.
04/06/2016 Version 2.1
General Updates

Small editorial update to the Root Port Error FIFO Read Register (Offset 0x154) section.

Added the Tandem Configuration section.

New Parameter Changes and Port Changes tables for the release added to the Migrating and Updating appendix.

11/18/2015 Version 2.0
General Updates

Updated the supported speed grades.

Updated the Limitations section in the Overview chapter.

Updated the description for m_axi_arready.

Added VCU108 to the Reference Boards section in the Debugging chapter.

09/30/2015 Version 2.0
General Updates

Updated for the core version 2.0.

Added support for Root Port configurations.

Added MSI-X signal support.

Updated the clock and reset diagrams.

Added the Configuration Control Register.

Clarified the Reference Clock input frequency as refclk for Virtex-7 devices, and sys_clk_gt for UltraScale devices.

Updated supported values and the defaults for the following parameters:
  • C_S_AXI_NUM_WRITE
  • C_S_AXI_NUM_READ
  • C_M_AXI_NUM_WRITE
  • C_M_AXI_NUM_READ

Added the PL_UPSTREAM_FACING bridge parameter.

Added the RX_Detect parameter.

Added the cfg_ltssm_state port.

Updated the Register Memory Map and Bridge Info Register tables.

Added the Enhanced Configuration Access table (ECAM).

06/24/2015 Version 1.1
General Updates

Moved performance and resource utilization data to Xilinx website.

Corrected C_NUM_MSI_REQ from attribute to signal.

Corrected the documented parameters: added top-level parameters, removed erroneous entries, and corrected parameter names, and descriptions.

Added the BAR Addressing section.

Corrected Example 2 (64-bit PCIe Address Mapping).

Added ports enabled with the Enable MSIX Capability Structure options selected to the Migrating and Upgrading chapter

Updated Vivado® Lab Edition to Vivado® Design Suite Debug Feature.

05/07/2015 Version 1.1
General Updates Minor editorial update: Corrected page footers.
04/01/2015 Version 1.1
General Updates

Specified that the narrow burst feature is not supported.

To Vivado IDE description, added new GT Settings tab, and PLL Selection, CORE CLOCK Frequency, PPM Offset between receiver and transmitter, Spread Spectrum clocking, Insertion loss at Nyquist, and Link Partner TX Preset parameters.

Added post-synthesis and post-implementation netlist simulation details.

Added Transceiver Debug information.

Updated Vivado lab tools to Vivado Lab Edition.

11/19/2014 Version 1.0
General Updates

Added UltraScale architecture placement constraint examples.

Updated the simulation procedures for Cadence Incisive Enterprise Simulator (IES), and Verilog Compiler Simulator (VCS).

Added important note regarding the recommended version of Mentor Graphics simulator to use to avoid simulation failure.

Minor edits.

10/01/2014 Version 1.0
Initial Release N/A