Root Port Interrupt Decode 2 Mask Register (Offset 0x164) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English
Note: This register is valid for XDMA Root Port Bridge only, and reserved for AXI PCIe3 Bridge.

The RootPort Interrupt Decode 2 Mask register controls whether INTx interrupt is checked by Interrupt decode bit 16 and also forwarded to interrupt_out in Interrupt Decode mode. The Root Port Interrupt Decode 2 Mask Register initializes to all zeros. The following table describes the register bits.

Table 1. Root Port Interrupt Decode 2 Mask Register
Bits Name Core Access Reset Value Description
15:0 Reserved RO 0 Reserved
16 INTA status RW 0

1 - INTA is checked by Interrupt Decode [16]

0 - INTA is not checked by Interrupt Decode [16]
17 INTB status RW 0

1 - INTB is checked by Interrupt Decode [16]

0 - INTB is not checked by Interrupt Decode [16]
18 INTC status RW 0

1 - INTC is checked by Interrupt Decode [16]

0 - INTC is not checked by Interrupt Decode [16]
19 INTD status RW 0

1 - INTD is checked by Interrupt Decode [16]

0 - INTD is not checked by Interrupt Decode [16]
31:20 Reserved RO 0 Reserved