Root Port Interrupt Decode 2 Register (Offset 0x160) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English
Important: This register is valid for XDMA Root Port Bridge only, and reserved for AXI PCIe3 Bridge.

The Root Port Interrupt Decode 2 Register reads from this location return INTx interrupt source status. Data from each read follows the format shown in the following table. For non-Root Port cores, reads return 0.

Table 1. Root Port Interrupt Decode 2 Register
Bits Name Core Access Reset Value Description
15:0 Reserved RO 0 Reserved
16 INTA status RO 0

1 - INTA is asserted. Keeps 1 till INTA Deassert is received.

0 - INTA is deserted. Keep 0 till INTA Assert is received.
17 INTB status RO 0

1 - INTB is asserted. Keeps 1 till INTB Deassert is received.

0 - INTB is deserted. Keep 0 till INTB Assert is received.
18 INTC status RO 0

1 - INTC is asserted. Keeps 1 till INTC Deassert is received.

0 - INTC is deserted. Keep 0 till INTC Assert is received.
19 INTD status RO 0

1 - INTD is asserted. Keeps 1 till INTD Deassert is received.

0 - INTD is deserted. Keep 0 till INTD Assert is received.
31:20 Reserved RO 0 Reserved