Root Port Interrupt FIFO Read Register 2 (Offset 0x15C) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The Root Port Interrupt FIFO Read Register 2 reads from this location return message payload for MSI Interrupts. The header information is presented in the Root Port Interrupt FIFO Read 1 register. The interrupt-handling flow is to read the Root Port Interrupt FIFO Read 1 register first, immediately followed by this register. For non-Root Port cores, reads return 0. For INTx interrupts, reads return zero.

Reads are non-destructive. Removing the message from the FIFO requires a write to either this register or the Root Port Interrupt FIFO Read 1 register (write value is ignored).

Table 1. Root Port Interrupt FIFO Read Register 2
Bits Name Core Access Reset Value Description
15:0 Message Data RWC 0 Payload for MSI messages.
31:16 Reserved RO 0 Reserved