Root Port MSI Base Register 1 (Offset 0x14C) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

The Root Port MSI Base register contains the upper 32-bits of the 64-bit MSI address (described in the following table). For EP configurations, read returns zero.

Table 1. Root Port MSI Base Register 1
Bits Name Core Access Reset Value Description
31:0 MSI Base RW 0

4 Kb-aligned address for MSI interrupts. In case of 32-bit MSI, it returns 0 but captures the upper 32-bits of the MSI address in case of 64-bit MSI.