Root Port MSI Base Register 2 (Offset 0x150) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The Root Port MSI Base register 2 (described in the following table) sets the address window in Root Port cores used for MSI interrupts. MemWr TLPs to addresses in this range are interpreted as MSI interrupts. MSI TLPs are interpreted based on the address programmed in this register. The window is always 4 Kb, beginning at the address indicated in this register. For EP configurations, a read returns zero. However, the Bridge core does not support MSI-X and multiple vector address, only single MSI is supported.

Table 1. Root Port MSI Base Register 2
Bits Name Core Access Reset Value Description
11:0 Reserved RO 0 Reserved
31:12 MSI Base RW 0 4 Kb-aligned address for MSI interrupts.