Root Port MSI Interrupt Decode 1 Mask Register (Offset 0x178)

Root Port MSI Interrupt Decode 1 Mask Register (Offset 0x178) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID

PG194

Release Date

2023-11-24

Version

3.0 English

The Root Port MSI Interrupt Decode 1 Mask register controls whether MSI interrupt vector 0-31 are forwarded to interrupt_out_msi_vec0to31 signal in Interrupt Decode mode. The Root Port MSI Interrupt Decode 1 Mask Register initializes to all zeros. The following table describes the register bits.

Table 1. Root Port MSI Interrupt Decode 1 Mask Register
Bits	Name	Core Access	Reset Value	Description
31:0	MSI Vector Status	RW	0	1 - This MSI vector is indicated in interrupt_out_msi_vec0to31 signal. 0 - This MSI vector is not indicated in interrupt_out_msi_vec0to31 signal. Bit index [x] indicates MSI vector x.