The AXI Bridge for AXI Bridge for PCI Express Gen3 and DMA/Bridge Subsystem for PCIe in AXI Bridge mode support Shared Logic and Shared clocking features that are available in the PCIe subcore IPs. Note that each device family contain different Shared Logic and/or Shared Clocking features that can be supported based on the IP configuration. More details about these features can be found in the “Designing with the Core” chapter in the following documents.
- For the Virtex 7 XT device, see Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023).
- For UltraScale devices, see UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156).
- For UltraScale+ devices, see UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).