Supported Configurations - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English
The following table lists the link widths, the required core clock frequency and speed grade.
Table 1. Minimum Device Requirements
Capability Link Speed Capability Link Width usr_clk

(MHz)

 Supported Speed Grades CXS Width

(bits)
Gen3 x8 250 All 256
x16 250

3E (VCCINT = 0.90V),

-2E (VCCINT = 0.85V), and

-2I (VCCINT = 0.85V)

 512
Gen4 x4 250 All 256
x8 250

-3E (VCCINT = 0.90V),

-2E (VCCINT = 0.85V), and

-2I (VCCINT = 0.85V)

 512