Tandem Configuration - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

Tandem Configuration utilizes a two-stage methodology that enables the IP to meet the configuration time requirements indicated in the PCI Express Specification. Multiple use cases are supported with this technology:

  • Tandem PROM: Load the single two-stage bitstream from the flash.
  • Tandem PCIe: Load the first stage bitstream from flash, and deliver the second stage bitstream over the PCIe link to the MCAP.
  • Tandem (PCIe) with Field Updates: After a Tandem PROM (UltraScale only) or Tandem PCIe (UltraScale or UltraScale+) initial configuration, update the entire user design while the PCIe link remains active. The update region (floorplan) and design structure are predefined, and Tcl scripts are provided.
  • Tandem + Dynamic Function eXchange: This is a more general case of Tandem Configuration followed by Dynamic Function eXchange (DFX) of any size or number of dynamic regions.
  • Dynamic Function eXchange over PCIe: This is a standard configuration followed by DFX, using the PCIe / MCAP as the delivery path of partial bitstreams.

To enable any of these capabilities, select the appropriate option when customizing the core. In the Basic tab:

  1. Change the Mode to Advanced.
  2. Change the Tandem Configuration or Dynamic Function eXchange option according to your particular case:
    • Tandem for Tandem PROM, Tandem PCIe or Tandem + Dynamic Function eXchange use cases.
    • Tandem with Field Updates ONLY for the predefined Field Updates use case.
    • DFX over PCIe to enable the MCAP link for Dynamic Function eXchange, without enabling Tandem Configuration.
Figure 1. Tandem Configuration or Dynamic Function eXchange Option

Tandem Configuration features are available for the Bridge core for all supported UltraScale and UltraScale+ devices.

For complete information about Tandem Configuration, including supported devices, required PCIe block locations, design flow examples, requirements, restrictions and other considerations, see Tandem Configuration in the UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) and UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213). For information on Dynamic Function eXchange, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).