Transceiver Debug - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English
Important: The ports in the Transceiver Control And Status Interface must be driven in accordance with the appropriate GT user guide. Using the input signals listed below may result in unpredictable behavior of the IP core.

The following table describes the ports used to debug transceiver related issues when a 7 series device is targeted.

Table 1. Ports Used for Transceiver Debug
Port I/O Width Description
pipe_txprbssel I 3 PRBS input
pipe_rxprbssel I 3 PRBS input
pipe_rxprbsforceerr I 1 PRBS input
pipe_rxprbscntrreset I 1 PRBS input
pipe_loopback I 1 PIPE loopback
pipe_rxprbserr O 1 PRBS output
pipe_rst_fsm O   Should be examined if PIPE_RST_IDLE is stuck at 0.
pipe_qrst_fsm O   Should be examined if PIPE_RST_IDLE is stuck at 0.
pipe_sync_fsm_tx O   Should be examined if PIPE_RST_FSM is stuck at 11'b10000000000, or PIPE_RATE_FSM is stuck at 24'b000100000000000000000000.
pipe_sync_fsm_rx O   Deprecated.
pipe_drp_fsm O   Should be examined if PIPE_RATE_FSM is stuck at 100000000.
pipe_rst_idle O   Wrapper is in IDLE state if PIPE_RST_IDLE is High.
pipe_qrst_idle O   Wrapper is in IDLE state if PIPE_QRST_IDLE is High.
pipe_rate_idle O   Wrapper is in IDLE state if PIPE_RATE_IDLE is High.
PIPE_DEBUG_0/gt_txresetdone O   Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_1/gt_rxresetdone O   Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals.The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_2/gt_phystatus O   Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_3/gt_rxvalid O   Generic debug ports to assist debug. These are generic debug ports to bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_4/gt_txphaligndone O   Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_5/gt_rxphaligndone O   Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_6/gt_rxcommadet O   Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_7/gt_rdy O   Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_8/user_rx_converge O   Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
PIPE_DEBUG_9/PIPE_TXELECIDLE O   Generic debug ports to assist debug. These generic debug ports bring out internal PIPE Wrapper signals, such as raw GT signals. DEBUG_0 to DEBUGT_9 are intended for per lane signals. The bus width of these generic debug ports depends on the number of lanes configured in the wrapper.
pipe_txinhibit I 1 Connects to TXINHIBIT on transceiver channel primitives.

The following table describes the ports used to debug transceiver related issues when an UltraScale™ ™ device is targeted.

Table 2. Ports Used for Transceiver Debug
Port I/O Width Description
gt_pcieuserratedone I 1 Connects to PCIEUSERRATEDONE on transceiver channel primitives
gt_loopback I 3 Connects to LOOPBACK on transceiver channel primitives
gt_txprbsforceerr I 1 Connects to TXPRBSFORCEERR on transceiver channel primitives
gt_txinhibit I 1 Connects to TXINHIBIT on transceiver channel primitives
gt_txprbssel I 4 PRBS input
gt_rxprbssel I 4 PRBS input
gt_rxprbscntreset I 1 Connects to RXPRBSCNTRESET on transceiver channel primitives
gt_txelecidle O 1 Connects to TXELECIDLE on transceiver channel primitives
gt_txresetdone O 1 Connects to TXRESETDONE on transceiver channel primitives
gt_rxresetdone O 1 Connects to RXRECCLKOUT on transceiver channel primitives
gt_rxpmaresetdone O 1 Connects to TXPMARESETDONE on transceiver channel primitives
gt_txphaligndone O 1 Connects to TXPHALIGNDONE of transceiver channel primitives
gt_txphinitdone O 1 Connects to TXPHINITDONE of transceiver channel primitives
gt_txdlysresetdone O 1 Connects to TXDLYSRESETDONE of transceiver channel primitives
gt_rxphaligndone O 1 Connects to RXPHALIGNDONE of transceiver channel primitives
gt_rxdlysresetdone O 1 Connects to RXDLYSRESETDONE of transceiver channel primitives
gt_rxsyncdone O 1 Connects to RXSYNCDONE of transceiver channel primitives
gt_eyescandataerror O 1 Connects to EYESCANDATAERROR on transceiver channel primitives
gt_rxprbserr O 1 Connects to RXPRBSERR on transceiver channel primitives
gt_dmonitorout O 17 Connects to DMONITOROUT on transceiver channel primitives
gt_rxcommadet O 1 Connects to RXCOMMADETEN on transceiver channel primitives
gt_phystatus O 1 Connects to PHYSTATUS on transceiver channel primitives
gt_rxvalid O 1 Connects to RXVALID on transceiver channel primitives
gt_rxcdrlock O 1 Connects to RXCDRLOCK on transceiver channel primitives
gt_pcierateidle O 1 Connects to PCIERATEIDLE on transceiver channel primitives
gt_pcieuserratestart O 1 Connects to PCIEUSERRATESTART on transceiver channel primitives
gt_gtpowergood O 1 Connects to GTPOWERGOOD on transceiver channel primitives
gt_cplllock O 1 Connects to CPLLLOCK on transceiver channel primitives
gt_rxoutclk O 1 Connects to RXOUTCLK on transceiver channel primitives
gt_rxrecclkout O 1 Connects to RXRECCLKOUT on transceiver channel primitives
gt_qpll1lock O 1 Connects to QPLL1LOCK on transceiver common primitives
gt_rxstatus O 3 Connects to RXSTATUS on transceiver channel primitives
gt_rxbufstatus O 3 Connects to RXBUFSTATUS on transceiver channel primitives
gt_bufgtdiv O 9 Connects to BUFGTDIV on transceiver channel primitives
phy_txeq_ctrl O 2 PHY TX Equalization control bits
phy_txeq_prese O 4 PHY TX Equalization Preset bits
phy_rst_fsm O 4 PHY RST FSM state bits
phy_txeq_fsm O 3 PHY RX Equalization FSM state bits (Gen3)
phy_rxeq_fsm O 3 PHY TX Equalization FSM state bits (Gen3)
phy_rst_idle O 1 PHY is in IDLE state
phy_rrst_n O 1 Synchronized reset generation by sys_clk
phy_prst_n O 1 Synchronized reset generation by pipe_clk

See UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213) for Transceiver Debug interface ports for Ultrascale+ devices when DMA/Bridge subsystem is enabled.