Transmit CCIX Core Interface (512-Bit) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The TX CCIX interface contains the ports through which all user application CCIX data is transmitted. The following table defines the ports in the 512-bit transmit CCIX interface.

Table 1. 512-Bit Transmit CCIX Interface Port Descriptions
Port Direction Width Description
s_axis_ccix_tx_tdata Input 512 Receives data to the core from the CCIX application.
s_axis_ccix_tx_tuser Input 100 This set of signals contains sideband information on TLP being transferred. These signals are valid when s_axis_cccix_tx_tvalid is High. Below The individual signals are defined in the following table.
s_axis_ccix_tx_tvalid Input 1 The CCIX application asserts this signal whenever it presents valid data on s_axis_ccix_tx_tdata.
ccix_tx_credit_gnt Output 1

This signal is asserted by core to release credits. The core has a total of eight TX credits. After VC1 link becomes active, the core first releases all the eight credits to the CCIX application, and then the core releases each credit as available. The CCIX application can transmit valid data when the application has credits available.

Note: If CCIX application drops valid between transmitting a TLP packet, the application must guarantee the continuation of TLP packet after ccix_tx_credit_gnt goes High at the core interface.

Or

The CCIX application waits to accumulate the needed amount of credits before transmitting TLP packet in order to avoid valid drop during the packet.

ccix_tx_credit_rtn Input 1 The CCIX application asserts this signal to return the credit to the core when the CCIX link goes to the deactivate state.
ccix_tx_active_req Input 1 This signal is asserted by the CCIX application to come out of deactive(stop) state and into active state. This signal needs to remain High for as long as CCIX application requires the link to be in the active state.
ccix_tx_active_ack Output 1 The core asserts this signal in response to the ccix_tx_active_req signal from the CCIX application when the core is ready to accept packets being sent.
ccix_tx_deact_hint Output 1 The core asserts this signal when the PCIe link goes through a link reset. The CCIX application must use this signal to return the credits and move to link deactive state.
Table 2. Sideband Signals in s_axis_ccix_tx_tuser (512-Bit Interface)
Bit Index Name Width Description
3:0 is_sop[3:0] 4

Signals the start of a TLP in this beat. The encoding is as follows

  • 0000: No new TLP starting in this beat.
  • 0001: A single new TLP starts in this beat. The start position is indicated by is_sop0_ptr.
  • 0011: Two new TLPs are starting in this beat.
    • is_sop0_ptr provides the start position of the first TLP.
    • is_sop1_ptr provides the start position of the second TLP.
  • 0111: Three new TLPs are starting in this beat.
    • is_sop0_ptr provides the start position of the first TLP.
    • is_sop1_ptr provides the start position of the second TLP.
    • is_sop2_ptr provides the start position of the third TLP.
  • 1111: Two new TLPs are starting in this beat.
    • is_sop0_ptr provides the start position of the first TLP.
    • is_sop1_ptr provides the start position of the second TLP.
    • is_sop2_ptr provides the start position of the third TLP.
    • is_sop3_ptr provides the start position of the forth TLP.
  • All other values: Reserved.
5:4 is_sop0_ptr[1:0] 2

Indicates the position of the first byte of the first TLP starting in this beat:

  • 00: Byte 0
  • 01: Byte 16
  • 10: Byte 32
  • 11: Byte 48
7:6 is_sop1_ptr[1:0] 2

Indicates the position of the first byte of the second TLP starting in this beat:

  • 00: Reserved
  • 01: Byte 16
  • 10: Byte 32
  • 11: Byte 48
9:8 is_sop2_ptr[1:0] 2

Indicates the position of the first byte of the second TLP starting in this beat:

  • 00: Reserved
  • 01: Reserved
  • 10: Byte 32
  • 11: Byte 48
11:10 is_sop3_ptr[1:0] 2

Indicates the position of the first byte of the second TLP starting in this beat:

  • 00: Reserved
  • 01: Reserved
  • 10: Reserved
  • 11: Byte 48
15:12 is_eop[3:0] 4

Signals that a TLP is ending in this beat. These inputs are set in the final beat of a TLP. The encoding are as follows:

  • 0000: No TLPs ending in this beat.
  • 0001: A single TLP is ending in this beat. The is_eop0_ptr[3:0] signal provides the offset of the last Dword of this TLP.
  • 0011: Two TLPs are ending in this beat.
    • is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP.
    • is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP.
  • 0111: Two TLPs are ending in this beat.
    • is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP.
    • is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP.
    • is_eop2_ptr[3:0] provides the offset of the last Dword of the third TLP
  • 1111: Two TLPs are ending in this beat.
    • is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP.
    • is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP.
    • is_eop2_ptr[3:0] provides the offset of the last Dword of the third TLP.
    • is_eop3_ptr[3:0] provides the offset of the last Dword of the fourth TLP.
  • All other values: Reserved.
19:16 discontinue[3:0] 4

This signal can be asserted by the user application during a transfer if it has detected an error in the data being transferred and needs to abort the packet. The core nullifies the corresponding TLP on the link to avoid data corruption.

The user logic can assert this signal in any beat of a TLP. It can either choose to terminate the packet prematurely in the cycle where the error was signaled, or continue until all bytes of the payload are delivered to the core.

The discontinue signal can be asserted only when s_axis_ccix_tx_tvalid is High. Thus, once asserted, it should not be deasserted until the end of the packet.

23:20 is_eop0_ptr[3:0] 4 Indicates the offset of the last Dword of the first TLP ending in this beat. This input is valid when is_eop[0] is asserted.
27:24 is_eop1_ptr[3:0] 4 Indicates the offset of the last Dword of the second TLP ending in this beat. This input is valid when is_eop[1] is asserted.
31:28 is_eop2_ptr[3:0] 4 Indicates the offset of the last Dword of the third TLP ending in this beat. This input is valid when is_eop[2] is asserted.
35:32 is_eop3_ptr[3:0] 4 Indicates the offset of the last Dword of the fourth TLP ending in this beat. This input is valid when is_eop[3] is asserted.
99:36 data_parity[63:0] 64

Odd parity for the 512-bit data. When parity checking is enabled in the core, the user logic must set bit i of this bus to the odd parity computed for byte i of s_axis_ccix_tx_tdata.

On detection of a parity error, the core nullifies the corresponding TLP on the link and reports it as an Uncorrectable Internal Error.