VSEC Header Register 2 (Offset 0x204) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The VSEC Header Register 2 (described in the following table) provides a unique (within a given vendor) identifier for the layout and contents of the VSEC structure, as well as its revision and length. VSEC Header Register 2 is part of the Bridge core that contains AXI Base Address Translation Configuration Registers which start immediately after VSEC Header Register 2 (Offset 0x208).

Table 1. VSEC Header Register 2
Bits Name Core Access Reset Value Description
15:0 VSEC ID RO   ID value uniquely identifying the nature and format of this VSEC structure.
19:16 VSEC REV RO 0x0 Version of this capability structure. Hardcoded to 0x0.
31:20 VSEC Length RO 0x038 Length of the entire VSEC Capability structure, in bytes, including the VSEC Capability register. Hardcoded to 0x038 (56 decimal).