DMA/Bridge Subsystem for PCI Express Product Guide (PG195) - 4.1 English

Document ID: PG195
Release Date: 2022-11-16
Version: 4.1 English

Introduction
Features
IP Facts
Overview
Feature Summary
Applications
Unsupported Features
Limitations
PCIe Transaction Type
PCIe Capability
Others
PCIe to DMA Bypass Master
User Interrupt in MSI-X Mode
Licensing and Ordering
Product Specification
Standards
Performance and Resource Utilization
Minimum Device Requirements
Configurable Components of the Subsystem
Target Bridge
H2C Channel
C2H Channel
AXI4-Lite Master
AXI4-Lite Slave
Host-to-Card Bypass Master
IRQ Module
Legacy Interrupts
MSI and MSI-X Interrupts
Config Block
XDMA Operations
Quick Start
Initial Setup For H2C and C2H Transfers
AXI-MM Transfer For H2C
AXI-MM Transfer For C2H
Descriptors
Descriptor Bypass
Poll Mode
DMA H2C Stream
DMA C2H Stream
Address Alignment
Length Granularity
Parity
Port Descriptions
XDMA Global Ports
PCIe Interface Signals
H2C Channel 0-3 AXI4-Stream Interface Signals
C2H Channel 0-3 AXI4-Stream Interface Signals
AXI4 Memory Mapped Read Address Interface Signals
AXI4 Memory Mapped Read Interface Signals
AXI4 Memory Mapped Write Address Interface Signals
AXI4 Memory Mapped Write Interface Signals
AXI4 Memory Mapped Write Response Interface Signals
AXI4 Memory Mapped Master Bypass Read Address Interface Signals
AXI4 Memory Mapped Master Bypass Read Interface Signals
AXI4 Memory Mapped Master Bypass Write Address Interface Signals
AXI4 Memory Mapped Master Bypass Write Interface Signals
AXI4 Memory Mapped Master Bypass Write Response Interface Signals
Config AXI4-Lite Memory Mapped Write Master Interface Signals
Config AXI4-Lite Memory Mapped Read Master Interface Signals
Config AXI4-Lite Memory Mapped Write Slave Interface Signals
Config AXI4-Lite Memory Mapped Read Slave Interface Signals
Interrupt Interface
Channel 0-3 Status Ports
Configuration Extend Interface Port Descriptions
Configuration Management Interface Ports
Descriptor Bypass Mode
Register Space
PCIe to AXI Bridge Master Address Map
PCIe to DMA Address Map
PCIe to DMA Address Format
PCIe to DMA Configuration Registers
H2C Channel Registers (0x0)
H2C Channel Identifier (0x00)
H2C Channel Control (0x04)
H2C Channel Control (0x08)
H2C Channel Control (0x0C)
H2C Channel Status (0x40)
H2C Channel Status (0x44)
H2C Channel Completed Descriptor Count (0x48)
H2C Channel Alignments (0x4C)
H2C Poll Mode Low Write Back Address (0x88)
H2C Poll Mode High Write Back Address (0x8C)
H2C Channel Interrupt Enable Mask (0x90)
H2C Channel Interrupt Enable Mask (0x94)
H2C Channel Interrupt Enable Mask (0x98)
H2C Channel Performance Monitor Control (0xC0)
H2C Channel Performance Cycle Count (0xC4)
H2C Channel Performance Cycle Count (0xC8)
H2C Channel Performance Data Count (0xCC)
H2C Channel Performance Data Count (0xD0)
C2H Channel Registers (0x1)
C2H Channel Identifier (0x00)
C2H Channel Control (0x04)
C2H Channel Control (0x08)
C2H Channel Control (0x0C)
C2H Channel Status (0x40)
C2H Channel Status (0x44)
C2H Channel Completed Descriptor Count (0x48)
C2H Channel Alignments (0x4C)
C2H Poll Mode Low Write Back Address (0x88)
C2H Poll Mode High Write Back Address (0x8C)
C2H Channel Interrupt Enable Mask (0x90)
C2H Channel Interrupt Enable Mask (0x94)
C2H Channel Interrupt Enable Mask (0x98)
C2H Channel Performance Monitor Control (0xC0)
C2H Channel Performance Cycle Count (0xC4)
C2H Channel Performance Cycle Count (0xC8)
C2H Channel Performance Data Count (0xCC)
C2H Channel Performance Data Count (0xD0)
IRQ Block Registers (0x2)
IRQ Block Identifier (0x00)
IRQ Block User Interrupt Enable Mask (0x04)
IRQ Block User Interrupt Enable Mask (0x08)
IRQ Block User Interrupt Enable Mask (0x0C)
IRQ Block Channel Interrupt Enable Mask (0x10)
IRQ Block Channel Interrupt Enable Mask (0x14)
IRQ Block Channel Interrupt Enable Mask (0x18)
IRQ Block User Interrupt Request (0x40)
IRQ Block Channel Interrupt Request (0x44)
IRQ Block User Interrupt Pending (0x48)
IRQ Block Channel Interrupt Pending (0x4C)
IRQ Block User Vector Number (0x80)
IRQ Block User Vector Number (0x84)
IRQ Block User Vector Number (0x88)
IRQ Block User Vector Number (0x8C)
IRQ Block Channel Vector Number (0xA0)
IRQ Block Channel Vector Number (0xA4)
Config Block Registers (0x3)
Config Block Identifier (0x00)
Config Block BusDev (0x04)
Config Block PCIE Max Payload Size (0x08)
Config Block PCIE Max Read Request Size (0x0C)
Config Block System ID (0x10)
Config Block MSI Enable (0x14)
Config Block PCIE Data Width (0x18)
Config PCIE Control (0x1C)
Config AXI User Max Payload Size (0x40)
Config AXI User Max Read Request Size (0x44)
Config Write Flush Timeout (0x60)
H2C SGDMA Registers (0x4)
H2C SGDMA Identifier (0x00)
H2C SGDMA Descriptor Low Address (0x80)
H2C SGDMA Descriptor High Address (0x84)
H2C SGDMA Descriptor Adjacent (0x88)
H2C SGDMA Descriptor Credits (0x8C)
C2H SGDMA Registers (0x5)
C2H SGDMA Identifier (0x00)
C2H SGDMA Descriptor Low Address (0x80)
C2H SGDMA Descriptor High Address (0x84)
C2H SGDMA Descriptor Adjacent (0x88)
C2H SGDMA Descriptor Credits (0x8C)
SGDMA Common Registers (0x6)
SGDMA Identifier Registers (0x00)
SGDMA Descriptor Control Register (0x10)
SGDMA Descriptor Control Register (0x14)
SGDMA Descriptor Control Register (0x18)
SGDMA Descriptor Credit Mode Enable (0x20)
SG Descriptor Mode Enable Register (0x24)
SG Descriptor Mode Enable Register (0x28)
MSI-X Vector Table and PBA (0x8)
Designing with the Subsystem
Clocking and Resets
Tandem Configuration
Customizing the Subsystem for Tandem Configuration
UltraScale Devices
UltraScale+ Devices
Supported Devices
UltraScale Devices
UltraScale+ Devices
Design Flow Steps
Customizing and Generating the Subsystem
Basic Tab
PCIe ID Tab
PCIe BARs Tab
PCIe MISC Tab
PCIe DMA Tab
Debug Options Tab
Shared Logic Tab
GT Settings Tab
Output Generation
Constraining the Subsystem
Relocating the Integrated Block Core
Simulation
Basic Simulation
AXI-MM Mode
AXI-ST Mode
Descriptor Bypass
PIPE Mode Simulation
Parameters for Custom PIPE Simulation
Synthesis and Implementation
Example Design
Available Example Designs
AXI4 Memory Mapped Default Example Design
AXI4 Memory Mapped with PCIe to AXI4-Lite Master and PCIe to DMA Bypass Example Design
AXI4 Memory Mapped with AXI4-Lite Slave Interface Example Design
AXI4-Stream Example Design
AXI4 Memory Mapped with Descriptor Bypass Example
Vivado IP Integrator-Based Example Design
User IRQ Example Design
Customizing and Generating the Example Design
Test Bench
Root Port Model Test Bench for Endpoint
Architecture
Test Case
Simulation
AXI4 Memory Mapped Interface
AXI4-Stream Interface
Descriptor Bypass Mode
AXI-MM Descriptor Bypass Mode Simulation
AXI-Stream Descriptor Bypass Mode Simulation with Loopback Design
Simulation Updates
Multi-Channels Simulation, Example Channel 1 H2C and C2H
Multi Descriptor Simulation
Test Tasks
GT Locations
Application Software Development
Device Drivers
Linux Device Driver
Using the Driver
Interrupt Processing
Legacy Interrupts
MSI Interrupts
MSI-X Interrupts
User Interrupts
Example H2C Flow
Example C2H Flow
Upgrading
New Parameters
New Ports
Debugging
Finding Help on Xilinx.com
Documentation
Debug Guide
Solution Centers
Answer Records
Master Answer Record for the Subsystem
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Hardware Debug
General Checks
Initial Debug of the DMA/Bridge Subsystem for PCIe
Using the Xilinx Virtual Cable to Debug
Overview
Host PC XVC-Server Application
Host PC XVC-over-PCIe Driver
XVC-over-PCIe Enabled FPGA Design
XVC-over-PCIe Through PCIe Extended Configuration Space (PCIe-XVC-VSEC)
XVC-over-PCIe Through AXI (AXI-XVC)
XVC-over-PCIe Register Map
PCIe Ext Capability Header
PCIe VSEC Header (PCIe-XVC-VSEC only)
XVC Version Register (PCIe-XVC-VSEC only)
XVC Shift Length Register
XVC TMS Register
XVC TDO/TDI Data Register(s)
XVC Control Register
XVC Status Register
XVC Driver and Software
Special Considerations for Tandem or Dynamic Function eXchange Designs
Using the PCIe-XVC-VSEC Example Design
Generating a PCIe-XVC-VSEC Example Design
System Bring-Up
Compiling and Loading the Driver
Compiling and Launching the XVC-Server Application
Connecting the Vivado Design Suite to the XVC-Server Application
Run Time Considerations
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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