AXI-MM Descriptor Bypass Mode Simulation - 4.1 English

1. The example design has a predefined descriptor for the H2C and C2H engine.
2. The H2C descriptor has 128 bytes of data, source address (Host) and destination address (Card).
3. The C2H descriptor has 128 bytes of data, source address (Card) and destination address (Host).
4. The test case writes incremental 128 bytes of data to the Host memory source address.
5. The PIO writes to the H2C engine Control register to start the transfer (0x0004).
6. The DMA reads data from the Host address and sends it to the Card block RAM destination address.
7. The PIO writes to the C2H engine Control register to start the transfer (0x1004).
8. The DMA reads data from the Card block RAM source address and sends it to the Host destination address.
9. The test case compares data for correctness.
10. The test case checks for the H2C and C2H descriptor completed count (value of 1).
11. The test case then disables the transfer by deasserting the Run bit (bit 0) in the Control register for the H2C and C2H engine (0x0004 and 0x1004).