The example design for the AXI4-Stream (AXI_ST) mode is a loopback design. On the user side the H2C ports are looped back to the C2H ports. First, the C2H transfer is started and the C2H DMA engine waits for data on the user side. Then, the H2C transfer is started and the DMA engine reads data from the Host memory and writes to the user side. Because it is a loopback, design data from H2C is directed to C2H and ends up in the host destination address.
H2C and C2H are setup with one descriptor each, and the total transfer size is 64 bytes.
Interrupts are not used in AMD Vivado™ Design Suite simulations. Instead, descriptor completed count register is polled to determine transfer complete.