AXI-Stream Descriptor Bypass Mode Simulation with Loopback Design - 4.1 English

1. The example design has a predefined descriptor for the H2C and C2H engine.
2. The H2C descriptor has 128 bytes of data, source address (Host) and destination address (Card).
3. The C2H descriptor has 128 bytes of data, source address (Card) and destination address (Host).
4. The test case writes incremental 128 bytes of data to Host memory source address.
5. The PIO writes to the C2H engine Control register to start the transfer (0x1004).
6. The C2H engine starts the DMA transfer but waits for data (loopback design).
7. The PIO writes to the H2C engine Control register to start the transfer (0x0004).
8. The H2C engine reads data from the Host address and sends it to Card.
9. The data is looped back to the C2H engine.
10. The C2H engine reads data from the Card and sends it to the Host destination address.
11. The test case compares data for correctness.
12. The test case checks for the H2C and C2H descriptor completed count (value of 1).
13. The test case then disables the transfer by deasserting the Run bit (bit 0) in the Control register for the H2C and C2H engine (0x0004 and 0x1004).

When the transfer is started, one H2C and one C2H descriptor are transferred in Descriptor bypass interface and after that DMA transfers are performed as explained in above section. Descriptor is setup for 64 bytes transfer only.