AXI4 Memory Mapped Interface - 4.1 English

First, the test case starts the H2C engine. The H2C engine reads data from host memory and writes to block RAM on user side. Then, the test case starts the C2H engine. The C2H engine reads data from block RAM and writes to host memory. The following are the simulation steps:

1. The test case sets up one descriptor for the H2C engine.
2. The H2C descriptor is created in the Host memory. The H2C descriptor gives data length 128 bytes, source address (host), and destination address (Card).
3. The test case writes data (incremental 128 bytes of data) in the source address space.
4. The test case also sets up one descriptor for the C2H engine.
5. The C2H descriptor gives data length 128 bytes, source address (Card), and destination address (host).
6. Write H2C descriptor starting address to register (0x4080 and 0x4084).
7. Write to H2C control register to start H2C transfer address (0x0004). Bit 0 is set to 1 to start the transfer. For details of control register, refer to H2C Channel Control (0x04).
8. The DMA transfer takes the data host source address and sends to the block RAM destination address.
9. The test case then starts the C2H transfer.
10. Write C2H descriptor starting address to register (0x5080 and0x5084).
11. Write to C2H control register to start the C2H transfer (0x1004). Bit 0 is set to 1 to start the transfer. For details of control the register, see C2H Channel Control (0x04).
12. The DMA transfer takes data from the block RAM source address and sends data to the host destination address.
13. The test case then compares the data for correctness.
14. The test case checks for the H2C and C2H descriptor completed count (value of 1).
15. The test case then disables transfer by deactivating the Run bit (bit0) in the Control registers (0x0004 and 0x1004) for the H2C and C2H engines.