AXI4 Memory Mapped Master Bypass Write Interface Signals - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. AXI4 Memory Mapped Master Bypass Write Interface Signals
Signal Name Direction Description
m_axib_wdata

[DATA_WIDTH-1:0]

O Master write data.
m_axib_wlast O Master write last.
m_axib_wstrb O Master write strobe.
m_axib_wvalid O Master write valid.
m_axib_wready I Master write ready.
m_axib_wuser

[DATA_WIDTH/8-1:0]

O Parity ports for read interface. This port is enabled only in Propagate Parity mode.