AXI4 Memory Mapped Master Bypass Write Response Interface Signals - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. AXI4 Memory Mapped Master Bypass Write Response Interface Signals
Signal Name Direction Description
m_axib_bvalid I Master write response valid.
m_axib_bresp[1:0] I Master write response.
m_axib_bid

[ID_WIDTH-1:0]

 I Master write response ID.
m_axib_bready O Master response ready.