When the PCIe® to AXI4-Lite master and AXI4-Lite slave interface are enabled, the generated example design (shown in the following figure) has a loopback from AXI4-Lite master to AXI4-Lite slave. Typically, the user logic can use a AXI4-Lite slave interface to read/write DMA/Bridge Subsystem for PCI Express® registers. With this example design, the host can use PCIe to AXI4-Lite Master (BAR0 address space) and read/write DMA/Bridge Subsystem for PCI Express® registers, which is the same as using PCIe to DMA (BAR1 address space). This example design also shows PCIe to DMA bypass Interface (BAR2) enabled.
Figure 1. AXI-MM Example with AXI-Lite Slave Enabled
