Address Alignment - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. Address Alignment
Interface Type Datapath Width Address Restriction
AXI4 MM 64, 128, 256, 512 None
AXI4-Stream 64, 128, 256, 512 None
AXI4 MM fixed address 1 64 Source_addr[2:0] == Destination_addr[2:0] == 3’h0
AXI4 MM fixed address 1 128 Source_addr[3:0] == Destination_addr[3:0] == 4’h0
AXI4 MM fixed address 1 256 Source_addr[4:0] == Destination_addr[4:0] == 5’h0
AXI4 MM fixed address 1 512 Source_addr[5:0] == Destination_addr[5:0]==6'h0
  1. For fixed address mode, you must set bit [25] in the control registers.