Basic Tab - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID

PG195

Release Date

2023-11-24

Version

4.1 English

The Basic tab for the DMA mode (Functional Mode option) is shown in the following figure.

Figure 1. Basic Tab for DMA Functional Mode

The options are defined as follows:

Functional Mode

Allows you to select between the following:

DMA (DMA Subsystem for PCIe).
AXI Bridge (AXI Bridge Subsystem for PCIe). The AXI Bridge option is valid only for AMD UltraScale+™ devices. For details about PCIe Bridge mode operation, see AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194). This document covers DMA mode operation only.

Mode

Allows you to select the Basic or Advanced mode of the configuration of subsystem.

Device /Port Type

Only PCI Express® Endpoint device mode is supported.

PCIe Block Location

Selects from the available integrated blocks to enable generation of location-specific constraint files and pinouts. This selection is used in the default example design scripts. This option is not available if an AMD Development Board is selected.

Lane Width

The subsystem requires the selection of the initial lane width. For supported lane widths and link speeds, see the 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054), Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023), UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156), or the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213) Higher link speed cores are capable of training to a lower link speed if connected to a lower link speed capable device.

Maximum Link Speed

The subsystem requires the selection of the PCIe Gen speed.

Reference Clock Frequency

The default is 100 MHz, but 125 MHz and 250 MHz are also supported.

Reset Source

You can choose between User Reset and Phy ready.

User reset comes from the PCIe core once link is established. When PCIe link goes down, User Reset is asserted and XDMA goes to reset mode. And when the link comes back up, User Reset is deasserted.
When the Phy ready option is selected, XDMA is not affected by PCIe link status.

GT DRP Clock Selection

Select either internal clock (default) or external clock.

GT Selection, Enable GT Quad Selection

Select the Quad in which lane 0 is located.

AXI Address Width

Currently, only 64-bit width is supported.

AXI Data Width

Select 64, 128, 256-bit, or 512-bit (only for UltraScale+). The subsystem allows you to select the Interface Width, as defined in the 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054), Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023), UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156), or the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)

AXI Clock Frequency

Select 62.5 MHz, 125 MHz or 250 MHz depending on the lane width/speed.

DMA Interface Option

Select AXI4 Memory Mapped and AXI4-Stream.

AXI4-Lite Slave Interface

Select to enable the AXI4-Lite slave Interface.

Data Protection

By default parity checking is disabled.

When Check Parity is enabled, XDMA checks for parity on read data from the PCIe and generates parity for write data to the PCIe.
When Propagate Parity is enabled, XDMA propagates parity to the user AXI interface. The user is responsible for checking and generating parity on the user AXI interface.

Tandem Configuration or Dynamic Function eXchange

Select the tandem configuration or Dynamic Function eXchange feature, if application to your design.

Recommended: AMD recommends that you select the correct GT starting quad before setting the link rate and width. Selecting line rate and width prior to selecting GT quad can have adverse effects.