C2H Channel Performance Data Count (0xCC) - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. C2H Channel Performance Data Count (0xCC)
Bit Index Default Access Type Description
31:0 32’h0 RO

pmon_dat_count[31:0]

Increments for each valid read data beat while running. See the Performance Monitor Control register (0xC0) bits Clear and Auto for clearing.