Config AXI4-Lite Memory Mapped Write Slave Interface Signals - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. Config AXI4-Lite Memory Mapped Write Slave Interface Signals
Signal Name Direction Description
s_axil_awaddr[31:0] I This signal is the address for a memory mapped write to the DMA from the user logic.
s_axil_awvalid I The assertion of this signal means there is a valid write request to the address on s_axil_awaddr.
s_axil_awprot[2:0] I Unused
s_axil_awready O Slave write address ready.
s_axil_wdata[31:0] I Slave write data.
s_axil_wstrb I Slave write strobe.
s_axil_wvalid I Slave write valid.
s_axil_wready O Slave write ready.
s_axil_bvalid O Slave write response valid.
s_axil_bready I Save response ready.