The Debug Options tab is shown in the following figure.
Figure 1. Debug Options Tab
- JTAG Debugger
- This option enables JTAG debugging.
- LTSSM State Debug Logic
- This option shows all the LTSSM state transitions that have been made starting from link up.
- In System IBERT
- This option is used to check and see the eye diagram of the serial link at the
desired link speed. For more information on In System IBERT, refer to
In-System IBERT LogiCORE IP Product Guide
(PG246).Important: This option is used mainly for hardware debug purposes. Simulations are not supported when this option is used.
- Add Mark Debug Utility
- This option adds predefined PCIe signals to with mark_debug attribute so
these signals can be added in ILA for debug purpose. Following is the list of
signals:
-
m_axis_cq_tdata -
s_axis_cc_tdata -
s_axis_rq_tdata -
m_axis_rc_tdata -
m_axis_cq_tuser -
s_axis_cc_tuser -
m_axis_cq_tlast -
s_axis_rq_tlast -
m_axis_rc_tlast -
s_axis_cc_tlast -
pcie_cq_np_req -
pcie_cq_np_req_count -
s_axis_rq_tuser -
m_axis_rc_tuser -
m_axis_cq_tkeep -
s_axis_cc_tkeep -
s_axis_rq_tkeep -
m_axis_rc_tkeep -
m_axis_cq_tvalid -
s_axis_cc_tvalid -
s_axis_rq_tvalid -
m_axis_rc_tvalid -
m_axis_cq_tready -
s_axis_cc_tready -
s_axis_rq_tready -
m_axis_rc_tready
-
- Enable Descrambler
- This option integrates encrypted version of the descrambler module inside the PCIe core, which is used to descrambler the PIPE data to/from PCIe integrated block in Gen3/Gen4 link speed mode only.
- PCIe Debug Ports
- With this option enabled, the following ports are available:
-
cfg_negotiated_width: cfg_negotiated_width_o -
cfg_current_speed: cfg_current_speed_o -
cfg_ltssm_state: cfg_ltssm_state_o -
cfg_err_cor: cfg_err_cor_o -
cfg_err_fatal: cfg_err_fatal_o -
cfg_err_nonfatal: cfg_err_nonfatal_o -
cfg_local_error: cfg_local_error_o -
cfg_local_error_valid: cfg_local_error_valid_o
-