The previous tables represents PCIe to AXI4-Lite Master, DMA, and PCIe to DMA Bypass for 32-bit and 64-bit BAR selections. Each space can be individually selected for 32-bits or 64-bits BAR.
The number of H2C channels is configured in the AMD Vivado™
Integrated
Design Environment (IDE). The H2C channel handles DMA transfers from the host to the
card. It is responsible for splitting read requests based on maximum read request size,
and available internal resources. The DMA channel maintains a maximum number of
outstanding requests based on the RNUM_RIDS, which is the number of
outstanding H2C channel request ID parameter. Each split, if any, of a read request
consumes an additional read request entry. A request is outstanding after the DMA
channel has issued the read to the PCIe RQ block to
when it receives confirmation that the write has completed on the user interface
in-order. After a transfer is complete, the DMA channel issues a writeback or interrupt
to inform the host.
The H2C channel also splits transaction on both its read and write interfaces. On the read interface to the host, transactions are split to meet the maximum read request size configured, and based on available Data FIFO space. Data FIFO space is allocated at the time of the read request to ensure space for the read completion. The PCIe RC block returns completion data to the allocated Data Buffer locations. To minimize latency, upon receipt of any completion data, the H2C channel begins issuing write requests to the user interface. It also breaks the write requests into maximum payload size. On an AXI4-Stream user interface, this splitting is transparent.
When multiple channels are enabled, transactions on the AXI4 Master interface are interleaved between all selected channels. Simple round robin protocol is used to service all channels. Transactions granularity depends on host Max Payload Size (MPS), page size, and other host settings.