| Subsystem Specifics |
| Supported Device Family
1
|
AMD UltraScale+™
, AMD UltraScale™
, 7 series
Gen2 devices |
| Supported User Interfaces |
AXI4 MM, AXI4-Lite, AXI4-Stream
|
| Resources |
See Resource Utilization web page. |
| Provided with Subsystem |
| Design Files |
Encrypted System Verilog |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
XDC |
| Simulation Model |
Verilog |
| Supported S/W Driver |
Linux and Windows Drivers
2
|
| Tested Design Flows
3
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 65443
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- For details, see Application Software Development and AR: 65444.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- For AMD Versal™
Adaptive SoC,
refer to
Versal Adaptive SoC DMA and Bridge Subsystem for PCI
Express Product Guide (PG344).
|