IRQ Block Channel Interrupt Enable Mask (0x18) - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. IRQ Block Channel Interrupt Enable Mask (0x18)
Bit Index Default Access Type Description
W1C

channel_int_enmask

Bit descriptions are the same as in IRQ Block Channel Interrupt Enable Mask (0x10).

The following figure shows the packing of H2C and C2H bits.

Figure 1. Packing H2C and C2H