PCIe DMA Tab - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English

The PCIe DMA tab is shown in the following figure.

Figure 1. PCIe DMA Tab
Number of DMA Read Channels
Available selection is from 1 to 4.
Number of DMA Write Channels
Available selection is from 1 to 4.
Number of Request IDs for Read channel
Select the max number of outstanding request per channel. Available selection is from 2 to 64.
Number of Request IDs for Write channel
Select max number of outstanding request per channel. Available selection is from 2 to 32.
Descriptor Bypass for Read (H2C)
Available for all selected read channels. Each binary digits corresponds to a channel. LSB corresponds to Channel 0. Value of one in bit position means corresponding channels has Descriptor bypass enabled.
Descriptor Bypass for Write (C2H)
Available for all selected write channels. Each binary digits corresponds to a channel. LSB corresponds to Channel 0. Value of one in bit position means corresponding channels has Descriptor bypass enabled.
AXI ID Width
The default is 4-bit wide. You can also select 2 bits.
DMA Status port
DMA status ports are available for all channels.