The PCIe ID tab is shown in the following figure.
Figure 1.
PCIe ID Tab
- Enable PCIe-ID Interface
- By enabling this option, PCIe_ID port is given as an input port, you are expected to connect to a proper value as desired.
For a description of these options, see the “Design
Flow Steps” chapter in the respective product guide listed below:
- 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)
- Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)
- UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
- UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)