The DMA/Bridge Subsystem for PCI Express® supports the PIPE mode simulation where the PIPE interface of the core is connected to the PIPE interface of the link partner. This mode increases the simulation speed.
Use the Enable PIPE Simulation option on the Basic page of the Customize IP dialog box to enable PIPE mode simulation in the current AMD Vivado™ Design Suite solution example design, in either Endpoint mode or Root Port mode. The External PIPE Interface signals are generated at the core boundary for access to the external device. Enabling this feature also provides the necessary hooks to use third-party PCI Express VIPs/BFMs instead of the Root Port model provided with the example design. See also PIPE Mode Simulation Using Integrated Endpoint PCI Express Block in Gen3 x8 and Gen2 x8 Configurations Application Note (XAPP1184).
The following tables describe the PIPE bus signals available at the top level of the core
and their corresponding mapping inside the EP core (pcie_top
) PIPE
signals.
PIPE mode simulations are not supported for this core when VHDL is the selected target language.
In Commands |
Endpoint PIPE Signals Mapping |
Out Commands |
Endpoint PIPE Signals Mapping |
---|---|---|---|
common_commands_in[25:0] | not used | common_commands_out[0] | pipe_clk 1 |
common_commands_out[2:1] | pipe_tx_rate_gt 2 | ||
common_commands_out[3] | pipe_tx_rcvr_det_gt | ||
common_commands_out[6:4] | pipe_tx_margin_gt | ||
common_commands_out[7] | pipe_tx_swing_gt | ||
common_commands_out[8] | pipe_tx_reset_gt | ||
common_commands_out[9] | pipe_tx_deemph_gt | ||
common_commands_out[16:10] | not used 3 | ||
|
Input Bus |
Endpoint PIPE Signals Mapping |
Output Bus |
Endpoint PIPE Signals Mapping |
---|---|---|---|
pipe_rx_0_sigs[31:0] | pipe_rx0_data_gt | pipe_tx_0_sigs[31: 0] | pipe_tx0_data_gt |
pipe_rx_0_sigs[33:32] | pipe_rx0_char_is_k_gt | pipe_tx_0_sigs[33:32] | pipe_tx0_char_is_k_gt |
pipe_rx_0_sigs[34] | pipe_rx0_elec_idle_gt | pipe_tx_0_sigs[34] | pipe_tx0_elec_idle_gt |
pipe_rx_0_sigs[35] | pipe_rx0_data_valid_gt | pipe_tx_0_sigs[35] | pipe_tx0_data_valid_gt |
pipe_rx_0_sigs[36] | pipe_rx0_start_block_gt | pipe_tx_0_sigs[36] | pipe_tx0_start_block_gt |
pipe_rx_0_sigs[38:37] | pipe_rx0_syncheader_gt | pipe_tx_0_sigs[38:37] | pipe_tx0_syncheader_gt |
pipe_rx_0_sigs[83:39] | not used | pipe_tx_0_sigs[39] | pipe_tx0_polarity_gt |
pipe_tx_0_sigs[41:40] | pipe_tx0_powerdown_gt | ||
pipe_tx_0_sigs[69:42] | not used 1 | ||
|