Parity - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English

Parity checking occurs one of two ways. Set the Parity Checking option in the PCIe DMA Tab in the AMD Vivado™ IDE during core customization:

When Check Parity is enabled, the DMA/Bridge Subsystem for PCIe checks for parity on read data from PCIe, and generates parity for write data to the PCIe.

When Propagate Parity is enabled, the DMA/Bridge Subsystem for PCIe propagates parity to the user AXI interface. You are responsible for checking and generating parity in the AXI Interface. Parity is valid every clock cycle when a data valid signal is asserted, and parity bits are valid only for valid data bytes. Parity is calculated for every byte; total parity bits are DATA_WIDTH/8.

  • Parity information is sent and received on *_tuser ports in AXI4-Stream (AXI_ST) mode.
  • Parity information is sent and received on *_ruser and *_wuser ports in AXI4 Memory Mapped (AXI-MM) mode.

Odd parity is used for parity checking. By default, parity checking is not enabled.