Note: This document
covers only DMA mode register space. For AXI Bridge mode, see the
AXI Bridge for PCI Express Gen3 Subsystem Product
Guide (PG194).
Configuration and status registers internal to the DMA/Bridge Subsystem for PCI Express® and those in the user logic can be accessed from the host through mapping the read or write request to a Base Address Register (BAR). Based on the BAR hit, the request is routed to the appropriate location. For PCIe BAR assignments, see Target Bridge.