Revision History - 4.1 English

• Added -2 supported speed grade for Gen3 x16 for architecture devices (PCIE4).
• Added Gen4 link speed details for Virtex AMD UltraScale+™ devices with high bandwidth memory (HBM).
• Added information about behavior for multiple channels to the H2C Channel section.
• Added information about access restrictions to the AXI4-Lite Slave.
• Updated the cfg_ext_read_received description.

• Updated the Descriptor Bypass Mode description to reflect that H2C and C2H descriptors have 128 bytes of data.
• Added the Tcl command for Post-Synthesis simulation for the example design.

Clarified that Tandem Configuration is not yet supported for Bridge mode in UltraScale+ devices.

Added limitation: For 7 series, PCIe access from Host system must be limited to 1DW (4 Bytes) transaction only.

Added clarifying text to the IRQ Module configuration component (Legacy Interrupts, and MSI and MSI-X Interrupts sections).

Editorial updates in the H2C Channel 0-3 AXI4-Stream Interface Signals tables, and C2H Channel 0-3 AXI4-Stream Interface Signals tables.

Added the dma_bridge_resetn signal to the Top-Level Interface Signals table.

Updated Register Name: IRQ Block Channel Interrupt Pending (0x4C)

Added Virtex UltraScale+ Devices with HBM (PCIE4C) minimum device requirements information.

Added Shared Logic support for 7 series Gen2 family devices.

Added clarifying text to the MSI Interrupt, MSI-X Interrupts, and User Interrupts sections.

Updated Minimum Device Requirements table for Gen 3 x8 support.

Added detail to the h2c_dsc_byp_ctl[15:0], and c2h_dsc_byp_ctl[15:0] port descriptions.

Added Timing Diagram for Descriptor Bypass mode.

Updated description for 11:8 bit index (Channel ID[3:0] field) in the PCIe to DMA Address Field Descriptions table.

Added new c_s_axi_supports_narrow_burst parameter to the “Upgrading” appendix.

PCIe AXI Bridge mode operation removed from this guide, and moved to AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194). This document (PG195) only covers DMA mode operation.

In the Tandem Configuration section, added instruction and device support information for UltraScale+ devices, and added device support information for UltraScale devices.

Updated the “Upgrading” appendix according to port and parameter changes for this version of the core.

Added Appendix D, “Using Xilinx Virtual Cable to Debug”.

Updated the [NUM_USR_INT-1:0] bit description details.

Updated the PCI Extended Tag parameter description.

Added a quick start for DMA C2H and H2C transfers in the Product Specification chapter.

Updated driver support, Windows driver is in pre-production.

Updated Identifier Version.

Added new GUI parameters: Reset Source, MSI-X Implementation

Location, and AXI outstanding transactions.

Added Vivado IP integrator-based example design.

Updated the Simulation and Descriptor Bypass Mode sections in the Test Bench chapter.

Added new parameters and ports to the Upgrading appendix.

Updated the core name to reflect two core functional modes: AXI Bridge Subsystem for PCIe (UltraScale+ only), and DMA Subsystem for PCIe (all other supported devices).

Organized the Customizing and Generating the Subsystem section (Chapter 4) according to the options available for the two functional modes.

Added Debug Options tab in the Vivado IDE to enable debugging options in the core.

Updated Identifier Version.

Added additional device family support.

Add support for use with the AMD Gen2 integrated block for PCIe core.

Added performance data to an Answer Record on the web.

Updated datapath width and restriction in the Address Alignment and

Length Granularity tables in the DMA Operations section.

Added Basic Vivado Simulation section.

Added AXI-MM Example with Descriptor Bypass Mode section.

Added additional supported 7 series evaluation board in Debugging appendix).

AXI4-Stream Writeback Disable Control bit documented