SGDMA Descriptor Control Register (0x10) - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. SGDMA Descriptor Control Register (0x10)
Bit Index Default Access Type Description
19:16 4’h0 RW

c2h_dsc_halt[3:0]

One bit per C2H channel. Set to one to halt descriptor fetches for corresponding channel.
15:4     Reserved
3:0 4’h0 RW

h2c_dsc_halt[3:0]

One bit per H2C channel. Set to one to halt descriptor fetches for corresponding channel.