The Shared Logic tab for IP in an AMD UltraScale™ device is shown in the following figure.
Figure 1. Shared Logic (UltraScale
Devices)
The Shared Logic tab for IP in an AMD UltraScale+™ device is shown in the following figure.
Figure 2. Shared Logic (UltraScale+
Devices)
For a description of these options, see Chapter 4, “Design Flow Steps” in the respective product guide listed below: