Simulation - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English

Simulation is set up to transfer one descriptor in H2C and one descriptor in C2H direction. Transfer size is set to 128 bytes in each descriptor. For both AXI-MM and AXI-Stream, data is read from Host and sent to Card (H2C). Then data is read from Card and sent to Host (C2H). Data read from Card is compared with original data for data validity.

Limitations:
  • Simulation does not support Interrupts. Test case just reads status and complete descriptor count registers to decide if transfer is completed.
  • Simulations are done only for Channel 0. In a future release, multi channels simulations will be enabled.
  • Transfer size is limited to 128 bytes and only one descriptor.
  • Root port simulation model is not a complete BFM. Simulation supports one descriptor transfer which shows a basic DMA procedure.
  • By default, post-synthesis simulation is not supported for the example design. To enable post-synthesis simulation, generate the IP using the following Tcl command:
    set_property -dict [list CONFIG.post_synth_sim_en {true}] [get_ips <ip_name>]
    Note: With this feature, functional simulation time increases to approximately 2.5 ms.