Vivado IP Integrator-Based Example Design - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
In addition to the RTL-based example designs, the IP also supports a AMD Vivado™ IP integrator-based example design. To use the example design:
  1. Create an IP integrator block diagram.
  2. Open the IP integrator workspace, as shown in the following figure.

  3. In order to add the DMA/Bridge IP to the canvas, search for DMA/Bridge (xdma) IP in the IP catalog.

    After adding the IP to the canvas, the green Designer Assistance information bar appears at the top of the canvas.



  4. Click Run Block Automation from the Designer Assistance information bar.

    This opens a Run Block Automation dialog box (shown in the following figure) which lists all the IP currently in the design eligible for block automation (left pane), and any options associated with a particular automation (right pane). In this case, there is only the XDMA IP in the hierarchy in the left pane. The right pane has a description and options available. The Options can be used to configure the IP as well as decide the level of automation for block automation.



The Run Block Automation dialog box has an Automation Level option, which can be set to IP Level or Subsystem Level.

IP Level
When you select IP level automation, the Block Automation inserts the utility buffer for the sys_clk input, connects the sys_rst_n input and pcie_mgt output interface for the XDMA IP, as shown in the following figure.

Subsystem Level
When you select subsystem level automation, the Block Automation inserts the necessary sub IPs on the canvas and makes the necessary connections. In addition to connecting the sys_clk and sys_rst_n inputs it also connects the pcie_mgt output interface and user_lnk_up, user_clk_heartbeat and user_resetn outputs. It inserts the AXI interconnect to connect the Block Memory with the XDMA IP through the AXI BRAM controller. The AXI interconnect has one master interface and multiple slave interfaces when the AXI4-Lite master and AXI-MM Bypass interfaces are enabled in the Run Block Automation dialog box. The block automation also inserts Block Memories and AXI BRAM Controllers when the AXI4-Lite master and AXI-MM Bypass interfaces are enabled.