XDMA Global Ports - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)

Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. Top-Level Interface Signals
Signal Name Direction Description
sys_clk I

7 series Gen2 and Virtex 7 Gen3: PCIe reference clock. Should be driven from the O port of reference clock IBUFDS_GTE2.

UltraScale: DRP clock and internal system clock (Half the frequency of sys_clk_gt if PCIe Reference Clock is 250 MHz, otherwise same frequency as sys_clk_gt frequency). Should be driven by the ODIV2 port of reference clock IBUFDS_GTE3.

sys_clk_gt I UltraScale only: PCIe reference clock. Should be driven from the O port of reference clock IBUFDS_GTE3. See the UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156), or UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).
sys_rst_n I Reset from the PCIe edge connector reset signal
axi_aclk O PCIe derived clock output for m_axi* and s_axi* interfaces. axi_aclk is a derived clock from the TXOUTCLK pin from the GT block; it is not expected to run continuously while axi_aresetn is asserted.
axi_aresetn O AXI reset signal synchronous with the clock provided on the axi_aclk output. This reset should drive all corresponding AXI Interconnect aresetn signals.
dma_bridge_resetn I Optional pin and available only when SOFT_RESET_EN parameter is set to TRUE. This pin is intended to be user driven reset when link down, Function Level Reset, Dynamic Function eXchange, or another error condition defined by user occurs. It is not required to be toggled during initial link up operation.
When used, all PCIe traffic must be in quiesce state. The signal must be asserted for longer than the Completion Timeout value (typically 50 ms).
  • 0: Resets all internal Bridge engines and registers as well as asserts the axi_aresetn signal while maintaining PCIe link up.
  • 1: Normal operation.

See Clocking and Resets for further instruction on using this signal.

user_lnk_up O Output Active-High Identifies that the PCI Express core is linked up with a host device.
msi_enable O Indicates when MSI is enabled.
msi_vector_width[2:0] O Indicates the size of the MSI field (the number of MSI vectors allocated to the device).
msix_enable O Indicates when MSI-X is enabled.