With the availability of several peripherals within PS, PCW provides an organized way to access these peripherals. The Address Fragmentation allows you to expand the peripherals based on the address space in which they are assigned within the AMD Zynq™ UltraScale+™ MPSoC. Lower LPD slaves, Upper LPD slaves, FPD slaves and others are few of the available choices. Based on the selection, only the selected segments will be shown up in the address editor in Vivado along with the addresses to which they will be mapped to the PL- master.
This way only the list of selected peripherals will appear in the address editor. This can be used where the requirement is to have more address space available for the PL components, rather than a single address block assigned to Zynq UltraScale+ MPSoC addressable components.
Notes:
1. High DDR segment is not enabled if the DDR size is less than or equal to 2GB.
2. When the DDR size is greater than 2GB, the High DDR segment can be used to have DDR addressed in a higher address space, this is limited to 4GB of DDR size.
3. You must have a 64-bit master in the PL in order to access higher address space above 4GB.
4. PCIE_HIGH1 (0x0600000000) and PCIE_HIGH2(0x8000000000) block are not open for PL masters because PL masters are not intended to use PCIE_HIGH blocks.
For more information, see the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .