Clock Configuration Columns for Output Clocks - 3.5 English

Zynq UltraScale+ MPSoC Processing System Product Guide

Document ID
PG201
Release Date
2023-06-16
Version
3.5 English

Name Name of the peripheral clock source.

Source – This is the source PLL for the corresponding peripheral. You can select different PLL sources using the drop-down menu.

FracEn – Fractional Enable for the respective PLL clock source. Used to achieve the exact user desired frequency.

Requested Freq (MHz) – This is the input frequency given to the corresponding peripheral. The values in this column are not applicable in the manual mode and should be ignored. These are used only in automatic mode.

Divisor 0 – Denotes the 1st stage 6-bit programmable divisor. The divisor value should be entered in the manual mode for the required output clock frequency.

Divisor 1 – Denotes the 2nd stage 6-bit programmable divisor. The divisor value should be entered in the manual mode for the required output clock frequency.

Actual Freq (MHz) – In Manual Mode, the actual frequency is a result of your selection of PLL Multiplier (M) and Divide (D) choices.

Range (MHz) – This is the Minimum/Maximum range of the frequency that the corresponding peripheral can work with.