Clocking - 3.5 English

Zynq UltraScale+ MPSoC Processing System Product Guide

Document ID
PG201
Release Date
2023-06-16
Version
3.5 English

There are four clock groups.

Main Clock Group (MCG). This group has five PLLs.

° I/O PLL

° RPU PLL

° APU PLL

° DDR PLL

° Video PLL

Secure Clock Group (SCG). This group has two PLLs.

° eFuse

° PMU

RTC Clock Group (RCG). This is Real Time Clock, a dedicated internal clock for RTC. The RTC clock group (RCG) provides a 32 KHZ clock to the RTC in the battery power domain (BPU). It is an extremely small clock domain compared with the other two clock groups. There is no clock divider required for this clock.

Interface Clock Group (ICG). This group has clocks that are provided externally, like clocks from physical-side interface (PHY) and PL.

PL side peripherals can be operated through a PL clock (FCLK_CLK0…3). They generate the frequency ranges from 0.1 to 1600 MHz.