Column Descriptions for Output Clocks - 3.5 English

Zynq UltraScale+ MPSoC Processing System Product Guide

Document ID
PG201
Release Date
2023-06-16
Version
3.5 English

Source – This is the source PLL for the corresponding peripheral. You can select different PLL sources using the drop-down menu

Requested Freq (MHz) – This is the input frequency you can give to the corresponding peripheral

Divisor 0 – Denotes the 1st stage 6-bit programmable divisor provided by the wizard in the auto mode

Divisor 1 – Denotes the 2nd stage 6-bit programmable divisor provided by the wizard in the auto mode

FracEn - Denotes the fractional clocking enable option to facilitate precise clocking

Actual Freq (MHz) – This is the actual frequency calculated by the Processor Configuration Wizard. The clocking algorithm works with multiple factors, peripherals, PLLs and priorities; therefore, in certain cases, the actual frequency might be different than the Input Frequency

Range (MHz) – This is the Minimum/Maximum range of the frequency that the corresponding peripheral can work with. In this mode, you must configure the M and D values to achieve the desired frequency. When this mode is enabled, the values requested through Output mode will be overwritten.

Note: In order to modify the clock frequencies/divisors, the corresponding clock must be enabled in the IO configuration.