DDR Traffic Class - 3.5 English

The PS DDR enables traffic classes in the controller via the DDRC.PCFGQOS0 and DDRC.PCFGWQOS0 registers. These registers assign DDRC traffic classes based on the incoming ARQOS/AWQOS signals coming from the PS interconnect override register or on the AXI transactions from individual peripherals. The traffic classes are set as per the following table:

The AXI slave interfaces by default are set to override an AXI QOS value of 0. This results in PS DDR best effort regardless of the PL AXI_QOS signal on the interface via the AFIFM register module. For more information, see the DDR QoS Controller section of Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .