Example Design - 3.5 English

Zynq UltraScale+ MPSoC Processing System Product Guide

Document ID
PG201
Release Date
2023-06-16
Version
3.5 English

This chapter gives an example of how to set up a DDR Configuration.

The PS Configuration Wizard (PCW), provides you with the means to configure the DDR controller for your specific DDR Memory Part in an easy and intuitive manner. The following procedure demonstrates how to build a complete DDR configuration using the PCW and taking as an example Micron's MT41K1G8SN-125:A.

1. To access the DDR configuration, select the DDR Configuration from the PCW.

Looking at the DDR Configuration page, notice that it is split into four sections, these are:

° Clocking Options

° DDR Controller Options

° DDR Memory Options

° Other Options

Figure 5-1: DDR Configuration

X-Ref Target - Figure 5-1

DDR_Configuration.PNG

2. From the DDR Configuration page, create a DDR Configuration using as an example the Micron MT41K1G8SN-125:A, which denotes a DDR3 device. For this example the focus is on the DDR Controller Options and DDR Memory Options .

Note: The Micron data sheet MT41K1G8SN-125:A content in This Figure through This Figure is provided with permission of Micron Technology Inc. [Ref 8]

Figure 5-2: Micron Data Sheet

X-Ref Target - Figure 5-2

ddr_data_sheet.PNG

Note: Content of This Figure used with permission by Micron Technology, Inc.
© 2010/09/04 Micron Technology, Inc., All Rights Reserved

3. Examine the first page of the data sheet in This Figure and in particular the device name. You can identify the information that is required in order to fill in the DDR Controller Options and DDR Memory Options sections of the DDR Configuration Page.

° The Device Part name provides a lot of information, for instance, 1G8 is the capacity of the device. In this case it is a 1 Gigabit Device by 8, which makes this an 8 Gigabit Device as shown as the first red rectangle This Figure . There is a more in-depth calculation in the next steps.

° The Device Part name also gives information as to the speed grade of the device. In this case it is designated as -125 as in 1.25 ns which is the maximum clock period in nanoseconds in this case and a CAS latency of 11 cycles for a DDR3-1600 Speed Bin as shown as the third red rectangle in This Figure . You will see a more in-depth calculation in the next steps.

° Using as an example the MT41K1G8SN-125:A device translates to the following.

- Capacity = 1 GBits x 8 = 8 GBits

- Speed Grade = -125
1.25 ns @CL =11(DDR3-1600)
1.25 ns clock cycle == operating frequency of 800 MHz

Figure 5-3: DDR Example Part Number

X-Ref Target - Figure 5-3

example_part_number.png

Note: Content of This Figure used with permission by Micron Technology, Inc.
© 2010/09/04 Micron Technology, Inc., All Rights Reserved

° The Micron data sheet in This Figure shows an example part number and how to identify specific information of interest. For MT41K1G8SN-125:A:

- Configuration is Row 2 (1 Gig x 8, 1G8)

- Speed Grade is Row 3 (-125, t CLK =1.25ns, CL = 11)

- Temperature is Row 2 (Industrial temperature, IT)

4. Examine the following figure . It is important to understand the addressing scheme.

Figure 5-4: Addressing

X-Ref Target - Figure 5-4

addressing_text.png

Note: Content of This Figure used with permission by Micron Technology, Inc.
© 2010/09/04 Micron Technology, Inc., All Rights Reserved

The device capacity is expressed in bits. In this case the capacity is based on the addressable range of the Row, Column and Banks.

Device Capacity = (Row Addressable Range x Column Addressable Range x Bank Addressable Range) x Arrangement

For MT41K1G8SN:A, Look at the second column of the Addressing table designated as 1 Gig x 8, this provides the following values:

° Row Addressable Range = A[15:0] = 2 16

° Column Addressable Range = A[11, 9:0] = 2 11

° Bank Addressable Range = BA[2:0] = 2 3 .

° Arrangement = 8 (i.e. 1Gig x 8)

With these values and the Device Capacity equation, gives the following:

° Device Capacity = 2 16 x 2 11 x 2 3 x 8 = 8589934592 = 0x200000000 = 8Gbits

5. Examine the Speed Bin and Operating Conditions in This Figure .

Figure 5-5: DDR3L-1600 Speed Bins

X-Ref Target - Figure 5-5

speed_bin.png

Note: Content of This Figure used with permission by Micron Technology, Inc.
© 2010/09/04 Micron Technology, Inc., All Rights Reserved

Figure 5-6: DDR3L-1600 Speed Bins

X-Ref Target - Figure 5-6

ddr_4_4_table_1.png

Note: Content of This Figure is used with permission by Micron Technology, Inc.
© 2010/09/04 Micron Technology, Inc., All Rights Reserved

This following information can be derived by looking at both Table 41 in This Figure and Table 1 in This Figure .

° The device supports 800 MHz (speed grade -125 [1/1.25ns]) operating frequency and because you are accessing a Double Data Rated (DDR) device the maximum transfer is 1600 Million Transfers per second. See Table 41. Row 1 in This Figure .

° Cas Latency (cycles) = Looking at Table 1 – 3rd Row, 3rd Column – Target tRCD – tRP - CL) CL = 11 cycles

° Cas Write Latency (CWL) == Using CL = 11 and looking at Table 41 we can determine that CLW is set at 8 cycles.

° RAS to DAS Delay (cycles) == tRCD/clock cycle = 13.75 ns/1.25 ns = 11 cycles

° tRC = 48.75ns

° tRASmin = 35ns

6. With that information, you can now complete the DDR Configuration page.

Figure 5-7: DDR Configuration

X-Ref Target - Figure 5-7

DDR_Configuration00004.PNG

Following are descriptions of the DDR Controller options:

° Memory Type : Type of memory interface. For more details about the individual resets, see the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .

° Components: Types of the components supported by the memory controller.

° Effective DRAM Bus Width: Data width for DDR interface, not including ECC data width.

° ECC: Enables Error correction code support. ECC is supported only for an effective DRAM buswidth of 32 bits and 64 bits.

7. Notice that the Memory Interface Device Frequency field has been auto-populated to keep the settings in sync.

8. In the DDR Memory Options section, change the Speed Bin option. As stated previously this is a DDR3-1600 Device. Click and select DDR3 1600K from the drop down list.

Notice that PCW has auto-populated a number of fields such as:

° CAS Latency : Changed to 11 cycles

° CAS Write Latency : Changed to 8 cycles

° Additive Latency : Additive latency setting in memory clock cycles.

° RAS to CAS Delay : Changed to 11 cycles

° Precharge Time : Changed to 11 cycles.

° tRC : Set to 48.75 nanoseconds

° tRASmin : Set to 35 nanoseconds

° tFAW : Set to 30 nanoseconds

Even though these settings have been auto calculated you are still able to further fine tune them for your own specific part. Looking back at the settings that were calculated when reviewing the DDR from the Micron spreadsheet, notice that the values match.

9. Continue by reviewing the rest of the settings from the previous calculations. Looking at the DRAM IC Bus Width , select 8 as a 1G8 memory which implies a “by 8” arrangement as shown.

10. For DRAM Device Capacity , based on the previous calculations, select 8192 MBits which is equal to 8 Gigabits as shown.

11. For Rank Address Count (bits) the Number of Rank address pins.

12. For Bank Address Count (bits) the Bank Addressable Range was 2 to the power of 3, therefore, keep 3 as the bits of Bank Address Count (bits) .

13. For the Row Address Count (bits) the Row Addressable Range was 2 to the power of 16, therefore, keep 16 as the bits for Row Address Count (bits) .

14. For the Col Address Count (bits) it was stated that the Column Addressable Range was 2 to the power of 11, therefore, select 11 bits for Column Address Count (bits) .

15. Having concluded the calculations, click OK and then Save the Project .

16. For other Options descriptions, see Other Options .