• Enable/Disable I/O Peripherals (IOP)
• Enable/Disable AXI Interfaces
• Multiplexed I/O (MIO) Configuration
• Extended Multiplexed I/Os (EMIO)
• PL Clocks and Interrupts, resets
• PS internal clocking
• Generation of System Level Configuration Registers (SLCRs)
• High Speed SerDes Configuration
• PS DDR Configuration
• Isolation Configuration
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LogiCORE IP Facts Table |
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|---|---|---|---|---|---|
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Core Specifics |
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Supported Device Family (1) |
Zynq UltraScale+ MPSoC |
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Supported User Interfaces |
Not Applicable |
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Resources |
Not Applicable |
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Provided with Core |
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Design Files |
Verilog |
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Example Design |
See Example Design . |
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Test Bench |
Not Provided |
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Constraints File |
Not Provided |
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Simulation Model |
Not Provided |
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Supported
|
N/A |
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Tested Design Flows (2) |
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Design Entry |
AMD Vivado™ Design Suite |
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Simulation |
Not Applicable |
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 66183 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete list of supported devices, see Vivado IP catalog.
2.
For the supported versions of the tools, see the
|
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