Full Power Domain Clocks - 3.5 English

Zynq UltraScale+ MPSoC Processing System Product Guide

Document ID
PG201
Release Date
2023-06-16
Version
3.5 English

Processor/Memory Clocks – Clock configuration for A53 CPU (ACPU), GPU, and DDR

Peripherals/IO Clocks – Clock configuration for high-speed peripheral devices.

System Debug Clocks – Clock configuration for debug modules: DBG_FPD,DBG_TRACE, and DBG_TSTMP